CDA-4101 Lecture 10 Notes

More detail about how buses work

The CPU pins are the focal point for what happens on the buses Three broad categories of pins type on processor: address data (input, output or both) control these are the only means of communication the processor has with the rest of the system

• power (+3.3V or +5V)
• ground
• clock signal
• bus control - outputs to memory and I/O devices
• interrupts - inputs from other devices
• bus arbitration
• coprocessor signaling - floating point, graphics, etc.
• miscellaneous - status, reset, backward compatibility

• internal vs. external
• multiple buses

bus protocol - the specification or agreement between al the devices about how they will communicate

• mechanical specifications - number of wires, connectors, etc.
• electrical specifications - voltages, timing, etc.
• bus control language

a bus transaction is a request from one device to another the requesting device acts as the controlling device and is called the master the request acts as the servicer and it called the slave the role a device takes in a bus transaction is what determines if it is a master or slave the same device can act as master and slave at different times.

many devices (especially CPUs) are designed to consume as little power as possible. their electrical signals are not that strong current traveling a long a long bus or being fed to multiple devices needs to be amplified bus driver connects a master to the bus and amplifies its signals bus receiver connects a slave to a bus bus transreceiver combination of driver and receiver for devices that can act as both master and slave

• like a CPU, the bus has a combination of address, data and control lines
• each line on the bus makes the bus take more physical space, increases the size of the connectors, and increases the cost
• there is an econmic tradeoff between the number address and number of data lines and the system cost
• PC architecture bus wound up being overly complicated as they went from 20 to 24 to 32 address lines due to backward compatability concerns

• two ways to get more data over the bus:
  1. more data lines
  2. faster bus speeds
• faster speeds are limited by bus skew
• it is difficult to get all the wire lengths and electrical characteristics exactly equal
• data traverses the bus at different speeds.
• limited by the slowest path
• backward compatability is also an issue with altering the bus width and/or speed

• using the same lines for both addressing and data
• less bus lines reduces cost, but extra control mechanisms slow it down

• synchronous bus - clock controlled, integral number of cycles for each operation (e.g., 33 MHz, 66 MHz, 100 MHz, 133 MHz, etc.
• asynchronous bus - no clock, more flexible (no timing dependencies) , more complicated control

• example: 40 MHz bus, 25 ns cycle time
• compare fast buses today, 133 MHz, with processor speeds, 2 GHz
• example: memory access: 40 ns
• crossing lines represent value change
• shaded areas are unimportant data
• this example has less timing critical values than a real designer has to consider

• if memory ws faster, we could remove the wait state
• if memory was slower, we might have to add more wait states
• wait time is not computed by the bus each time there is a request: it is a fixed quantity that ensures the CPU can never try to read data before it is available
• therefore, there needs to be no extra control signals between the memory and CPU signalling when the data is ready.
• CPU grabs data blindly and so as long as timing is right, there are no problems
• if you tweak your computer's BIOS setting to remove wait states that are needed, you will get an unstable machine
• wait states set in the BIOS will depend on the memory speed

• integral clock intervals results in always having to round-up times.
• asynchronous bus will take exactly the amount required.
• requires extra control signals and coordination between amster and slave
• most buses are synchronous: simpler design, a lot of existing investment in this area

• All the previous discussion ignored the situation where there are more than a single master and single slave on the bus
• since the whole idea of a bus is to allow many devices to connect to a single common set of wires, we have to make sure only one master-slave pair is operating at a given time
• bus arbitration is the mechanism to ensure there are no conflicts on the bus
• two classes of arbitration: centralized and decentralized

• uses a bus arbiter to manage control of the bus
• a single request line as a wired-OR of all devices
• arbiter only knows either: no requests or >= 1 request
• a daisy-chained bus grant line
• first device that requested bus stops grant propogation
• "closeness" of device to the arbiterdetermines the priority

• "closeness" priority can be arbitray and is inflexible
• duplicate the request-grant lines for each priority level
• attatch devices to desired request-grant lines

• often a third line (an acknowledgement line) is used to signal when the bus has been grabbed
• this allows the bus arbiter and other devices to start negotiating the next bus grant (in parallel with the current bus access)
• when first device is finished, it negates the acknowledgement line to let the next in line use the bus

• does not require a bus arbiter
• arbitration handled implicitly by the rules the devices follow for accessing the bus

• each device on a separate request line
• each request line has a priority
• all devices monitor all request lines
• requires a lot of bus lines
• number of devices limited to number of priority request lines in the bus
• eliminates bus arbiter

• only need three lines, regardless of the number pf devices
• "busy" line asserted by current bus master
• daisy-chained arbitration line wire to +Vcc
• +Vcc is propogated through the devices until a device wants the bus
• device wanting bus, check "busy" line, and the incoming arbitration line
• if bus is idle and +Vcc on arbitration line, it negates the outgoing arbitration line, whch propogates through all devices
• winner asserts "busy" and reasserts its outgoing arbitration line
• priority determined by "closeness" to +Vcc source

• transfering block of data (especially contiguous data) can often be done by slave device much faster than a series of individual requests
• e.g., loading entire cache lines uses consecutive memory addresses and we have seen how memory can do these more quickly in sequence
• extra signal line for block transfers

as you will see in operating systems, a common issues with concurrent programs is ensuring two programs (or two processors) do not try to access the same data at the same time. you can keep a flag to indicate that data is in use, but you wind up with the same problem, only now concerning simultaneous access to the flag the read, modify, write of a memory location requires many steps, and if these steps are interleaved in the wrong way, you get the wrong results for two parallel accesses to properly synchronize programs and/or processors requires having an atomic operation for modifying a memory location atomic simply means that it is done as a single indivisible operation, so it is impossible for two things to modify it at the same time "read-modify-write" bus cycle ensures that the processor can read, modify and write to memory with nothing interrupts it. this is yet another specialized bus state

• interrupts work much like bus requests:
  • multiple devices could interrupt at the same time
  • usually a priority scheme on devices
• instead of a centralized bus arbiter, there is usually an interrupt controller
• the interrupts lines are part of the bus

• connected to up to 8 I/O controller
• 8259A connected to CPU "INT" line
• when CPU ready is acknowledges with "INTA"
• then 8259A send device number as data, whch requires a special bus cycle
• CPU used device number to index into a table of interrupt vectors that will handle interrupt
• various other features: e.g., disabling interrupts
• can cascade chips to get more devices: PC hardware uses 2 which really just gives 15 interrupts (details of how to do this not shown)