CDA-4101 Lecture 11 Notes

• Pentium II Memory Bus
• PCI Bus
• USB

• front side bus - connects CPU to memory and other devices (usually more than one of these)
• back side bus - connects CPU to level 2 (L2) cache.
  • back side bus is much faster
  • runs as the CPU clock speed (or some fraction of it)
  • individual back-side buses help eliminate a bottleneck in multiple CPU systems

• dedicated front side memory bus with hub to connect to other buses
• Pentium IV is 400 MHz (Pentium III was 133 MHz)
• nowadays, most processor have the back-side bus in silicon on the CPU chip itself (this started circa PIII)

• memory requests called transactions
• each transaction has a number of phases (i.e., stages of the pipeline)
• pipelining requires separate hardware for each stage
• processor needs separate hardware to manage each stage
• need separate pins for each stage

Stages/Phases: bus arbitration - not always needed, e.g., CPU can keep the bus for consecutive turns without asking request - puts the address on the bus, put the request type (e.g., word or block transfer) and asserts a signal when all rrequest lines are valid error reporting - request lines include parity lines, so if there is a parity error, it can be reported by the device. (Note it only does error detection.) snoop - needed only in multiprocessor systems to ensure cache consistency response - indicates when the slave (memory) is ready, to accept or send data data - sending of the actual data to/from memory

• PCI = perhipheral component interconnect
• developed around 1990 by Intel to address increasing needs for more bus bandwidth
• they put the rights to it into the public domain to encourage vendors to support it
• processor independent
• 256 Byte local device memory accessible to other devices for configuration (i.e., allows plug-n-play installation)
• synchronous
• address and data lines are multiplexed to keep pin count down
• allows 32 or 64 bit operation
• versions:
  • PCI 1.0 - 33 MHz (32 bits)
  • PCI 2.0 - 66 MHz or 133 MHz (64 or 32 bits)
  • PCI-X (3.0) - first ones just coming out

• transactions take 3 cycles:
  • cycle 1 - master puts address on lines
  • cycle 2 - master removes address and bus is (if reading) turned around in preparation for data
  • cycle 3 - data is put on bus
• if slave cannot respond on cycle 3, it insterts wait states
• block transfer of unlimited sizes are allowed

• centralized (separate chip or part of another bus control chip)
• each device has dedicated two lines to arbiter:
  1. bus request
  2. bus grant
• device asserts the request and waits until the grant line is asserted.
• arbitration algorithm not specified by PCI specification
• bus granted for one transaction (which is more than one cycle)
• bus master can keep the bus for a subsequent transaction if there is no other bus request
• if the bus arbiter ever negates the bus grant line, the bus master must relinquish it on the next cycle

• for low-speed I/O devices
• keyboard, mouse, scanners, printers, cameras, etc.
• simplify addition/configuration of low-speed devices
  • same cable/connector
  • installable while computer running (and without reboot)
• Bandwidth: 1.5 MB/sec
• root USB hub plugs into main (e.g., PCI) bus
• cables plug into hub and can go to devices or expansion hubs
• cable has 4 wires: 2 data, one power, one ground
• new device generates and interrupt
• USB interrupt handler finds out what this new device is and how much bandwidth it needs
• more details in book