CDA-4101 Lecture 16 Notes

• this is exactly the same as the one we looked at in previous section
• 6 bits of ALU control
  • F0 and F1 - selects the ALU function: AND, OR, NOT or ADD
  • INVA - complement A input (one's complement)
  • ENA - enable the A input (else zero)
  • ENB - enable the B input (else zero)
  • INC - lowest order carry in bit (allows adding 1)
• Not all 64 combinations of the ALU input control do something useful.
• two ALU status output bits
  • N - negative flag
  • Z - zero flag

Here are some of the useful possible combinations of ALU control signals: F0 F1 ENA ENB INVA INC Function 0 1 1 0 0 0 A 0 1 0 1 0 0 B 0 1 1 0 1 0 A' 1 0 0* 1 0 0 B' 1 1 1 1 0 0 A + B 1 1 1 1 0 1 A + B + 1 1 1 1 0 0 1 A + 1 1 1 0 1 0 1 B + 1 1 1 1 1 1 1 B - A 1 1 0 1 1 0* B - 1 1 1 1 0 1 1 -A 0 0 1 1 0 0 A AND B 0 1 1 1 0 0 A OR B 0 1 0 0 0 0 O 1* 1 0 0 0 1 1 0 1 0 0 1 0 -1 Minus means two's complement ("-")

Holding Register (H)is the left ALU input. To load, you must pass something on B bus through ALU and shifter without modification and then store it in H. Shifter has two control inputs: SLL8 - Shift Left Logical, will shift ALU contents left by one byte, adding zeroes to low order 8 bits. SRA1 - Shift Right Arithmetic, shift the ALU contents one bit to the right, but leaving the most significant byte (the sign bit) unchanged You can read and write the same register on a single cycle. The contents are put on B bus early in cycle time is allowed for ALU and Shifter to operate then toward the end of the cycle, the edge-triggered registers will load

• falling edge of clock starts the data path cycle
• rising edge of the clock latches in the results from C bus
• Making all this work is the hardware designer's job
• the clock width, the propogation delays, etc. must all be fast enough so that everything works

Two ports into memory 32 bit port 8 bit port 32-bit port: (Data Cache interface) MAR - Memory Address register specifies the memory address to use for a memory operation (LOAD or STORE) MDR - Memory Data Register serves as destination or source for LOAD and STORE operations note that you cannot put the MAR contents on the B bus 8-bit port: (Instruction Cache interface) PC - Program Counter serves as the address pointer into memory MBR - Memory Buffer Register serves as destination for memory contents (i.e., opcodes and their other fields) MBR only loads single byte because IJVM op-codes are only a single byte, not 32 bits. can only read from memory into the MBR register cannot write from C bus to MBR register

• MAR contains word addresses
• PC contains byte addresses
• A 3 in PC refers to memory address 3 (the fourth byte) , but a 3 in MAR refers to memory location 12 (the 4th word)
• All other registers that contain addresses will hold word addresses
• the machine's memory is really byte oriented and expects byte addresses.
• to convert MAR word addresses to byte addresses, just wire the low order two bits to zero and shift address left two bits. (same as multiplying by 4)

Two ways to put the one byte MBR onto the B bus: unsigned - MBR into low order 8 bits and zeroes in upper 24 bits signed - MBR into low order 8 bits and duplicate the sign bit in all upper 24 bits. i.e., treat as a signed integer and just convert it from an 8 bit represetnation to a 32 bit representation, e.g., 0000 0101 => 0000 0000 0000 0000 00000 0000 0000 0101 1100 0101 => 1111 1111 1111 1111 11111 1111 1100 0101 (called sign extension) the two control lines into the MBR register select one of the two ways to do this.

need 29 control signals to operate the full data path (and memory) 9 signals to control writing from C bus into regsiters 9 signals to control putting registers onto B bus 8 signals to control the ALU and Shifter 2 signals to signal memory read/write via MAR and MDR (not shown) 1 signal to indicate memory fetch via PC and MBR ( not shown) values on these 29 control lines will dictate the exact operation for one cycle of the data path

• the timing of the memory operations are not so intuitive, so this is the trickest part
• the bulk of the data path cycle is devoted to get the right memory address in MAR or PC
• the memory signals are not asserted until after the rising edge of the clock when MBR and MDR are loaded
• memory takes time, and with short clock pulse, it will not be available in cycle 2
• we assume it will always be available by the end of cycle 2 (dealing with variable lengths memory fetches is much more complicated)
• therefore: if on cycle 1 you want to read from memory, the data from memory will not be available for use until cycle 3
• You can access MBR or MDR in cycle 2, but you will get the old value

• You can perform back-to-back memory reads
• three memory reads in a row is pointless since you will overwrite some data before it is ever used

we may want to have the ALU output latched into more than one register we cannot put two registers on the B bus at the same time There are 9 control signal defining which register gets on the B bus We can encode the 9 B bus signals as a binary number and only need 4 control signals we use a decoder between these 4 signals and the 9 real control signals we can now control the data path with just 24 control signals (29-9+4) Binary Value Register Enabled 0 MDR 1 PC 2 MBR 3 MBRU 4 SP 5 LV 6 CPP 7 TOS 8 OPC 9 - 15 none

• suppose we had a 24 bit register that at any given point in time held exactly the values we wanted to control the data path
• to operate the data path we could load this 24 bit register, that pulse the data path clock to get the selected computation started
• it may take multiple data path cycles to do something interesting (i.e., executing a single ISA-level instruction)
• by having this 24 bit register go through the proper sequence of values, we can get the data path to function as we please

• since we will need a sequence of this 24 bit register's values to do something useful, we will also need some field to help keep track of where we can find the next group of 24 bit signals
• We will add 9 bits to the register that will hold an address where the next signals are stored.
• this is not an address from main memory, but an address in the control store for the microcode (details of how this works come later)
• we also add 3 more bits (JAM) that will serve as status flags when we need to have branch instructions whose next instruction will depend on the results of part of the data path state (details of how these are used will come later)
• Therefore, a single microinstruction will be exactly these 36 bits of information

• most of the microarchitecture should be familiar and understood
• there are a few elements in the microarchitecture that have not yet been explained (e.g., MIR, MPC, high-bit, JMPC)
• on the left is the data path
• on the right is the control section (to be discussed in detail subsequently)
• by the end, all of this should be understood

• transitor behavior (given)
• gates from transistors
• gates to combinational modules (decoders, multiplexers, shifters, comparators, adders, ALU, etc.)
• gates to sequential circuits (latches, flip-flops)
• sequential circuits to memory components (registers, RAM, ROM, etc.)
• combinational modules and memory components to data path
• last layer: full blown microarchitecture