CDA-4101 Lecture 17 Notes

• so far we shown how a single set of 36 bits (a microinstruction) can control the data path for one cycle, but have omitted how we can control and sequence a series of microinstructions
• a sequencer is the mechanism used to step through the series of microinstruction required to implement a single ISA instruction
• The two key things the sequencer must produce on each cycle:
  1. the state of every control signal in the system (i.e., the 24 signals controlling the data path)
  2. the address of the next microinstruction (e.g., the 9 address bits and the 3 condition codes (JAM))

• here we are using the term "control store" to distinguish the location of the microprogram from the location of ISA instruction which are in main memory
• it is not the sort of control stores we referred to when discussing early microprogramming hardware
• the actual hardware used to store the microinstructions is not crucial at this point: assume it is fast enough for the Mic-1 clock cycle.
• abstractly, think of the control store as containing the complete microprogram (all the microinstructiosn needed to implement the entire IJVM ISA)
• the control store may be a memory module (i.e., a microprogrammed architecture) or it could be built out of gates.
• For the Mic-1, the control store contains 512 words (or cells) consisting of 36 bit microinstructions (cell size is 36 bits)
• we will not need all 512 words (to be explained later)
• Note that the reason we defined needing 9 address bits in the microinstructions is that 2⁹ = 512, which is the size of the control store

• High-level languages and even ISA languages have implicit sequencing: the order of instructions, by default, proceeds sequentially in the order they are stored in memory (unless a branch instruction explicitly says otherwise.
• The Mic-1 microprogram uses explicit sequencing where every instruction explicitly includes the address of the next instruction to follow (though branches can alter this too)
• explicit sequencing is usually faster, but requires longer word lengths

just like we need a program counter (PC) and instruction register (MBR) to be able to execute an ISA program, we need similar registers to be able to execute the microprogram The MPC is the MicroProgram Counter: this is really not a counter, but simply a register holding the 9 bit address of the next microinstruction The MIR is the MicroInstruction Register: holds the currently executing microinstruction The MPC will contain the 9 bit address field of the microinstruction, with a possible altering from the JAM field bits if branching

Mic-1 Control Section

clock cycle starts with falling edge of clock MIR loaded from control store according to address contained in MPC (MIR register consists of trailing edge triggered flip-flops) Δw is the time it takes for the MIR to load and have stable outputs Δx is the time it takes for the control signals to propogate, data from the registers to be stable on the A and B buses, and the ALU/Shifter control signals to have ALU operation configuration stable Δy is the time it take for the ALU input values to propogate through the ALU and shifter and for the N and Z ALU outputs to be stable Δz is the time it takes for the ALU/Shifter outputs to propagate to the C bus (register input pins) At the rising edge of the clock: the contents of the C bus are loaded into the appropriate registers (as determined by the MIR fields); the ALU outputs N and Z are latched into a pair of one-bit flip-flops if needed, memory data is latched into MDR or MBR registers a short time after the rising edge, while the clock is still high, MPC gets its value we are then back where we started and this continues as long as there is power to the circuits

Mic-1 Control Section

• the microprogram uses explicit sequencing, and in general consecutive instructions are not located in consecutive control store addresses
• in order to support branching instructions that are conditional on the results of a computation (e.g., branch if result is zero), the three bits of the JAM field are used (JAMN, JAMZ and JMPC)
• if all three of the JAM bits are zero in a microinstruction, then the address of next microinstruction will always be the same and the 9 address bits of that microinstruction
• If one or more of the JAM bits are set, then there is a chance that the next microinstruction address will differ from the microinstruction's 9 bit address field

"High Bit" box in diagram contains the logic to compute the MPC's high-order bit this allows the next microinstruction's address to be determined (altered) by the results of an ALU computation in particular, the ALU outputs N and Z can be used to alter the next microinstruction address need 1-bit flip-flops for N and Z because after rising edge of clock, B Bus is no longer being driven, so we must assume ALU output is not valid (we use N and Z to determine the value of MPC after the rising edge of the clock. Let NEXT_ADDRESS[8] be the high-order bit of the address field for a microinstruction, then the truth table for the outputs of the "High Bit" box are ("+" means logical OR): JAMN JAMZ High Bit Output 0 0 NEXT_ADDRESS[8] 0 1 NEXT_ADDRESS[8] + Z 1 0 NEXT_ADDRESS[8] + N 1 1 NEXT_ADDRESS[8] + Z + N the idea is that by changing the high-order bit, you can change the address and thus the next instruction fetched from the control store. The high order bit function should be (see next slide for details): HighBit = (JAMZ · Z) + (JAMN · N) + NEXT_ADDRESS[8] since high-order value of MPC comes either directly from a microinstruction, or is OR'ed with something that is '1', if the microinstruction already had the high-order address set to '1', there is really no need to have any concern about the values of the N and Z ALU outputs (since it will not change the value of MPC.) The effective value of the high order bit (assuming NEXT_ADDRESS[8] = 0) is: HighBit = (JAMZ · Z) + (JAMN · N)

N Z JAMN JAMZ High Bit 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 This gives us the equation: HighBit = (JAMZ · Z) + (JAMN · N)

• for a given microinstruction, there are only two possible next instructions:
  1. the address encoded directly in the microinstruction
  2. the address encoded in the microinstruction plus 0x100

the third JAM bit is JMPC and when it is set, the low order 8 bits of the microinstruction's address field is logically OR'ed with the contents of the MBR typically we only want the contents of MBR, so we set the low-order bits of the microinstruction's address field to 0x00. we can set the high-order (i.e., 9th bit) of the address field to either 0 or 1 (we discuss later what all of this means)

JMPC MBR[i] NEXT_ADDRESS[i] MPC[i] 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 This gives us the equation: MPC[i] = NEXT_ADDRESS[i] + (JMPC · MBR[i])

• OR'ing with the MBR allows multi-way branching where the next address can be any one of 2⁸ = 256 possible values of MBR
• this allows us to use the op-code of an ISA instruction to index into the control store
• for a given op-code, its value indexing into the control store will be the first microinstruction needed to implement that ISA instruction
• it first fetches the op-code from main memory into the MBR then uses this to pull out of the control store the beginning of the microcode sequence necessary to implement this ISA instruction