CDA 3103 Pestaina FALL 2017
CDA 3103 .. Fundamentals of Computer Systems
FALL 2017
Norman Pestaina
Table Of Contents
General Information
- Instructor: Norman Pestaina .. Office ECS 340 .. Phone (305) 348-2013
.. Email pestaina@cs.fiu.edu
- Office Hours: Fall 2017
- Prerequisite : C or better in COP 2210 or equivalent.
- Description :
Common Course Syllabus ...
Topics Outline
- Textbook : Introduction to Computing Systems, Patt & Patel ..
Web-Page
Back to the top
Policies
Class Policies
Back to the top
Schedules
Class Meetings & Tests (Revised)
Back to the top
Exercises
Chapter 2
- Number Bases
- Integer Representation
- IEEE Short Real
- Bit Manipulation
- Problems: 2.20, 2.21, 2.22, 2.23, 2.24, 2.25, 2.36, 2.37, 2.38, 2.39, 2.50, 2.54
Chapter 3
- 2-Level AND-OR Circuits
- Decoders
- Multiplexers
- Adders ..
Adder-Subtractor
- Problems: 3.4 .. 3.7, 3.12, 3.14, 3.18, 3.24, 3.28, 3.30, 3.32, 3.34
Chapter 5
- Operate Instructions
- Addressing Modes
- Machine Language Programming
- Problems: 4.2, 4.8, 4.10, 4.12, 5.4, 5.24, 5.26, 5.30
Chapter 7
- 2-Pass Assembly
Back to the top
Assignments
Program Identification Paragraph
To be included at the start of all program files
- Sunday 11/19 - Machine Language
Specification ..
Division Algorithm ..
Data Files: ..
verse ..
rhyme
- Wednesday 11/29 - Assembly Language
Specification ..
Start-up Code ..
Solution
- Sunday 12/10 - Assembly Language
Specification ..
Start-up Code
Back to the top
Tests
- Test1 Tuesday, September 26
Data Representation: Chapter 2
- Test2 Tuesday, October 24
Digital Logic Circuits: Chapter 3
- Final FIU Finals Week Schedule
Computer Systems: Chapters 4, 5, 7, 8, 9, 10
Back to the top
Notes
- Data Representation (Chapter 2)
- Number Bases Binary & Hexadecimal ..
Conversion Checker
- Table Some Powers of 2
- Decimal -- Binary conversion ..
Sum of Powers ..
Repeated Division
- Integer Representations ..
2's Complement Signed & Unsigned Integer, Overflow
- Real Numbers IEEE Short Real
- Logical Operators AND, OR, XOR, Bit-manipulation ..
Problem 2.36
- Patt & Patel, Appendix E ASCII Codes, Powers, Prefixes ..
String Formats
- Digital Logic & Circuits (Chapter 3)
- 2-Level AND-OR ... Majority Function ...
Carry & oVerflow Flags
- Combinational Circuits Decoder & Multiplexer
- Memory Addressing Decoder Application
- Instruction Decoding Decoder Application
- Half & Full Adders Logic Diagrams
- R-S and D Latches Simplified Truth Tables
- The Instruction Cycle (Chapter 4)
- Instruction Cycle
- LC-3 Instructions Register Transfer Notation / Data-Path Implementation
- Programming the LC-3 (Chapter 5)
- LC-3 ISA Instruction Set Architecture ..
Instruction Formats
- Operate Instructions ..
Exercises: (Patt & Patel, p 123)
- Data Movement ..
Instructions ..
PC-Relative ..
Indirect & Base-Register ..
LDI & LDR ..
Exercises: (Patt & Patel, p 129)
- Control Instructions ..
BRanch
- Figure 5.12 Counted Loop / Traversal (Patt & Patel, p 134) ..
Flow-Chart, Illustration, Solution
- Figure 5.17 Character-count Program (Patt & Patel, p 140) ...
Register Allocation ...
Algorithm & Program
- Assembly Language Programming (Chapter 7)
- Assembly Example ..
source code ..
symbol table ..
listing file
- Odd Parity Example Program with Subroutine
- Shift Instructions Logical, Arithmetic, Circular ..
Right Shift Algorithm
- Extended Multiplication Algorithm & Trace
- Extended Division Algorithm & Trace
- I/O Polling & Interrupts (Chapter 8, 10.1, 10.2)
- Input (Polling)
- Output (Polling)
- Interrupts Generating the Interrupt Signal
- Interrupts Saving State, Transition, RTI
- C Language Implementation (Sections 12.5, 13.2, 13.3, 14.3)
- Assignment referencing variables
- Control Structures if, while, for
- Function call & return Textbook example
Back to the top
Grades
Class Grade Components
| Test 1 | Test2 | Test 3 | Assignments |
| 25% | 25% | 35% | 15% |
Grading Scale
| Letter Grade | Minimum Score |
| A | 90 |
| A- | 87 |
| B+ | 84 |
| B | 80 |
| B- | 75 |
| C+ | 70 |
| C | 65 |
| D | 45 |
Back to the top